This invention relates to reset signals. More particularly, this invention relates to routing reset signals throughout an intellectual property (IP) block during the same clock cycle.
Programmable logic resource technology is well known for its ability to allow a common hardware design (embodied in an integrated circuit) to be programmed to meet the needs of many different applications. Known examples of programmable logic resource technology include programmable logic devices (PLDs) and field programmable gate arrays (FPGAs).
To facilitate the use of programmable logic resources in certain applications, intellectual property (IP) blocks are coupled to programmable logic resource core circuitry. In one application, an IP block is a block of logic or data that supports a multi-channel input/output protocol such as high speed serial interface (HSSI) communications. HSSI communications includes industry standards such as, for example, XAUI, InfiniBand, 1G Ethernet, FibreChannel, Serial RapidIO, and 10G Ethernet. In a multi-channel input/output protocol, data transfers to and from programmable logic resource core circuitry and an IP block over multiple channels. For example, for the 10GBASE-X standard, which has a throughput of 10 Gigabits per second, the IP block has four channels that support data transfers of up to 2.5 Gigabits per second through each channel.
A reset signal, which can be asynchronous or synchronous, is typically routed to a central block where the reset signal goes through some reset logic and then fans out to all the channels in the IP block. When programmable logic resource core circuitry is coupled to the IP block, the programmable logic resource core circuitry sends the reset signal and other control signals to the IP block. The control signals direct the operation of the reset logic in order to conserve power during non-operational periods.
Several problems often arise with known methods of routing reset signals. The use of an asynchronous reset signal can cause different channels, or different blocks within the same channel, to come in or out of reset during different clock cycles. For example, an asynchronous reset signal that is sent to the IP block towards the end of a clock cycle may not get routed to all the channels by the end of that clock cycle. The use of an asynchronous reset signal limits the amount of time available for the signal to be routed to all the channels.
Resistance-Capacitance (RC) skew can cause additional delays in the routing of the reset signal to all the channels. RC is a time constant that refers to the time for a signal to travel between two locations. The longer the interconnect line from the central block to a channel in the IP block, the greater the propagation delay in the interconnect line, and the larger the RC skew. Further RC skews can be introduced in the distribution of the reset signal to different blocks within each channel. As a result, RC skew can lead to different channels, or different blocks within the same channel, coming in or out of reset during different clock cycles.
When the IP block is coupled with programmable logic resource core circuitry, the IP block needs to be in reset mode when the programmable logic resource is in the power-up or programming phases. The reset logic in the IP block is therefore typically controlled by control signals and/or configuration bits (e.g., configuration random access memory) from the programmable logic resource core circuitry. However, the control signals and/or configuration bits are vulnerable to glitches, which sometimes cause the reset logic to inadvertently enter or exit reset mode. A glitch is an unstable signal that makes a false transition (e.g., a signal that is supposed to be a binary “0” changes to a binary “1” before changing back to binary “0”). A glitch can occur due to racing between control signals during power-up or due to unstable configuration bits during programming. Racing occurs when two signals that originate from the same location propagate through different paths at different speeds.
As clock speeds continue to increase with newer technology, the issue of skew becomes more significant. The smaller the clock period, the more difficult it becomes to ensure that an entire IP block gets reset within the same clock cycle. In addition, because control signals and/or configuration bits from the programmable logic resource core circuitry are used to control the reset logic in the IP block, the problem of glitching continues to be a problem.
In view of the foregoing, it would be desirable to provide a skew-tolerant, glitch-free reset distribution apparatus and method for an IP block that supports a multi-channel input/output protocol.